Method for forming a metal extrusion free via

ABSTRACT

A process whereby elimination of metal extrusion through the via-barrier layer into the base of etched via holes is accomplished by controlling the process temperature of the via-barrier deposition to less than 400° C., and preferably to about 380° C. By eliminating the cause of metal extrusions, i.e., excessive thermally induced stresses on the metal confined biaxially by the dielectric via walls, the resulting defect-free vias are independent of the barrier thickness. The method is applicable to different metal stacks, and in turn, yield and reliability of the device is significantly enhanced.

FIELD OF THE INVENTION

[0001] The present invention relates to the manufacture of semiconductordevices, and more particularly to a method for forming vias insemiconductor devices.

BACKGROUND OF THE INVENTION

[0002] A continuing trend in semiconductor manufacturing is to make morepowerful and complex integrated circuit devices in a smaller area.Manufacturers achieve this objective by making individual feature sizessmaller and by locating these features closer together. Millions ofactive and passive devices, such as transistors, capacitors, andresistors are formed on a semiconductor substrate, such as silicon.These devices are isolated from each other on the substrate and laterare interconnected to form functional circuits. The quality of theseinterconnecting structures drastically affects the performance, andreliability of the completed circuits.

[0003] Often the interconnections are fabricated as a multilayerstructure having alternating layers of patterned metal and dielectricmaterials. The dielectric layers, frequently a form of silicon oxide,serve to separate the conductors, both vertically and horizontally, andvery small, vertical metal filled vias provide a means ofinterconnection between the metal levels. Performance of theinterconnections and dielectric must be precise and predictable in orderto provide a stable device.

[0004] In multilevel structures, the metal conductors may include a baselayer, a bulk conductor layer, and a capping layer, and the sum of theselayers is referred to as a metal stack. The metal stack is formed on adielectric layer, typically by sputtering, and then through the use ofphotolithographic techniques is etched to define the interconnectingstructure. Aluminum and aluminum alloys are often used as the bulkconductors in metal stacks.

[0005] As a result of the small size and complexity of vias,particularly for 0.35 micron and smaller technology, fabrication andintegrity often present a significant challenge to the manufacture,yield, and reliability of modern ultra large scale integrated circuits.

[0006] A simplistic via structure, as shown in FIG. 1, typicallyincludes a horizontal metal interconnection layer 101, most frequentlycomprised of aluminum, copper, or an aluminum alloy, one or moredielectric layers 102, usually some form of silicon dioxide, and aconductive metal plug 103 in the via, such as tungsten (W). In complexdevices, the metal level may be comprised of multiple layers ofmaterial, including currently popular titanium (Ti) and titanium nitride(TiN) which sandwich the conductive interconnection metal. The layers104, 105 serve multiple purposes which may include adhesion promotion,anti-reflection, and an aid in defining grain structures. Also, it hasbeen found that for proper orientation and formation of the TiN layer,it is necessary to first provide a clean surface of a titanium metallayer 105 which acts as a seed layer.

[0007] However, due to the interaction of aluminum and/or copper withother materials, a barrier layer 107 is usually provided between themetal interconnection layer and via plug. A typical via-barrier layer107, such as CVD deposited TiN which conforms to the inner surfaces ofthe via prior to forming the tungsten plug.

[0008] Obviously, misalignment of the metal stack can lead to exposureof the plug metal, and in turn to corrosion during subsequentprocessing. Poor coverage of the metal by the barrier metal can lead tovoids in the interconnection resulting from the tungsten source gasinteracting with aluminum. A number of other via failure mechanisms havebeen disclosed, along with proposed corrective procedures.

[0009] A more subtle yield loss related to via integrity has plagued theindustry, wherein via resistance may be marginally high, but moreimportantly an instability in the operating frequency has lead to bothyield and operating failures of the device. Such subtle failures aredifficult to detect and to control, but stress induced extrusion ofaluminum into the via has been identified in “Reflow of AlCu into Viasduring CVD TiN Barrier Deposition”, A, Oliva, et. al., ISRM2000, andBesser, et al in U.S. Pat. No. 5,789,315 (1998) as one contributor tosuch device reliability degradation.

[0010] A schematic drawing of a metal extrusion failure is illustratedin FIG. 2. The metal conductor 201 having a relatively high coefficientof thermal expansion is constrained and put into a state of compressionby the dielectric layers 202 of the via which have a much lowerexpansion coefficient. During thermal excursions, some of the metalstress may be relieved by an extrusion 206 through the barrier layers204 into the base of the via. While it is agreed that the failure isrelated to a thermally induced compressive stress in the metal linewhich causes the metal to extrude into the via to relieve stress, aclear solution for elimination of the defect has not been previouslyidentified.

SUMMARY OF THE INVENTION

[0011] It is an object of the current invention to provide a method forelimination of metal extrusions through the barrier layers of etched viaholes in multilevel integrated circuit devices.

[0012] It is an object of the invention to identify the root cause ofstress induced extrusions into vias, and to provide a method foreliminating the source of the failure.

[0013] It is an object of the invention to provide an improvedmanufacturing process for via barrier formation.

[0014] It is an objective of the invention to provide a manufacturingprocess which does not slow throughput.

[0015] It is an object of the invention to provide a manufacturingprocess for elimination of metal extrusions through the barrier layer,and into the via which is not related, and dependent upon a secondvariable or process.

[0016] It is an object of the invention to provide a method formanufacture of semiconductor devices which improves yield andreliability.

[0017] It is an object of the invention to provide a method forelimination of stress induced metal extrusions into vias which isapplicable to different metal stacks.

[0018] It is further an objective of the invention to provide a methodof eliminating stress induced metal extrusions into vias which is notdependent on barrier thickness.

[0019] It is an object of the invention to provide an interconnectionmetallization, including titanium aluminide, wherein good integrity ofthe via barrier against metal extrusions is exhibited.

[0020] The above and other objectives of the invention will be met bydisclosing a process whereby metal extrusion through the via barrierlayer into the base of an etched via holes is eliminated. Temperature ofthe in process wafer, and that of the via barrier deposition iscontrolled at less than 400° C., and preferably to about 380° C.,thereby decreasing compressive stresses on the metal at the process stepwhere the failure is manifested.

[0021] By eliminating the cause of metal extrusions, i.e., excessivethermally induced stresses on the metal confined biaxially by thedielectric via walls, the resulting defect free vias are independent ofthe barrier thickness, the method is applicable to different metalstacks, and in turn yield and reliability of the device is significantlyenhanced.

BRIEF DESCRIPTION OF THE FIGURES

[0022]FIG. 1 is a cross sectional view of a via structure. (prior art)

[0023]FIG. 2 is a cross section of a via having a metal extrusionthrough the barrier layers. (Prior art)

[0024]FIG. 3 is a cross section of via of a preferred embodiment of thecurrent invention.

[0025]FIG. 4a is a cross section of a metal stack of a preferredembodiment of the current invention.

[0026]FIG. 4b is a cross section through a reacted metal stack andetched via.

[0027]FIG. 4c is a cross section through a reacted metal stack andfilled via of the current invention.

DETAILED DESCRIPTION OF THE DRAWINGS

[0028] The cross section of a via known to prior art, as illustrated inFIG. 1, is similar to that of the current invention. However, inpractice, it should be recognized that the layers are not perfectlysmooth, that the thickness of each layer may not be uniform, and thatthe features may not be as well aligned, as shown. Further, a moredetailed look at a cross section of a via of a preferred embodiment ofthe current invention, as shown in FIG. 3 includes a reacted layer oftitanium aluminide 304 in the metal stack. The titanium aluminide,primarily existing as TiAl₃, has advantages of serving as a via etchstop, an electromigration resistance improvement, and as a barrieragainst aluminum extrusions or hillocks. These advantages of thetitanium aluminide layer are not novel, and are not a subject of theinvention; but integrity of the layer, that of the total via, and of thevia barrier against metal extrusions is critical, and is the subject ofthe invention. Lacking integrity of the reacted metal layer and the viabarrier, the metallurgical junctions may be unstable due to the presenceof metal extrusions and the aluminide interface. The disturbed interfacecan react and form voids under the via due to a volume reductionassociated with the titanium aluminide reaction. Further, aluminum inthe interconnection line can diffuse away from the junction and resultin mechanically induced stress migration.

[0029] In the preferred embodiment, the metal stack includes theinterconnection line 301 of aluminum (Al) doped with copper (Cu), andsandwiched between reactive titanium (Ti) sticking layers. A titaniumnitride (TiN) 306 or silicon oxynitride layer on the first surface 311of the metal stack serves as an anti-reflective coating (ARC).

[0030] A sticking layer of titanium 308 lies directly under the CVDdeposited titanium nitride via barrier layer 307 which covers both theside walls and bottom of the etched via hole. The via has been patternedand etched into a dielectric material 302, comprised of one or morelayers of an oxide. The via hole in filled with a tungsten plug 303.

[0031] Process steps involved in via formation for a multilevelintegrated circuit device of the current invention are as follows. Themetal stack, as shown in FIG. 4a, is deposited on an interlayerdielectric substrate. The stack includes a titanium layer 402 ofapproximately 140 Angstroms thickness on one major surface 461 of theclean, oxide free aluminum alloy layer 401, and about 200 Angstroms oftitanium on the second surface 462. A TiN, silicon oxynitride or otherantireflective coating (ARC) 406 is deposited atop the exposed surface.The aluminum interconnection line 401 is reacted with a very clean, andoxide free titanium to form a layer of titanium aluminide 412 (FIG. 4b)when annealed at 425° C. The metal stack is patterned and etched usingknown technology.

[0032] As shown in FIG. 4b, an interlayer dielectric 402 preferablyincludes deposited layers of high density plasma (HDP) 4021, and atetraethyl ortho silicate (TEOS) 4022 oxides which surround thepatterned metal line 401. The dielectric is patterned and etched to forma via-hole 410 using existing technology, and is subsequently planarizedby chemical mechanical polish. A typical metal degas process at 350° C.follows.

[0033] In FIG. 4c, a titanium seed layer 408 is deposited at arelatively low temperature in the via, and insitu a TiN film is CVDdeposited to provide the via-barrier 407 prior to filling the via holewith CVD deposited tungsten plug 403.

[0034] It is the thermal excursion during high temperature CVD TiNvia-barrier deposition which must be carefully controlled to avoidexcessive compressive stress on the metal from breaking through therelatively thin via-barrier layer. According to this invention,temperature of the substrate and of the via-barrier deposition iscontrolled to about 380° C. for successful elimination of metalextrusion through the barrier. The tungsten plug will confine the metalexpansion and preclude extrusion through the via-barrier once it hasbeen deposited.

[0035] The process step wherein the metal extrusion into the via occurshas been confirmed by analyses showing Al/Cu, Ti, and F in the anomalousextrusion. Further, transmission electron micrograph (TEM) analysesshows that the titanium layer was underneath the extrusion, indicatingthat the extrusion occurred during barrier deposition. Further, CVD TiNis found on top of the metal extrusions, thus confirming that extrusionsdo not occur as a function of the CVD W plug deposition, but do occurduring CVD titanium nitride deposition, which typically is a hightemperature process.

[0036] Therefore, the key to elimination of metal extrusions in etchedvia holes is to control the process temperatures, so that the relativelyhigh expansion metal is not excessively stressed by the confining lowexpansion dielectric layers, to the point that the metal breaks throughthe via-barrier layer prior to filling the via.

[0037] Besser and Cheung, U.S. Pat. No. 5,789,315, which is includedherein by reference, recognized a significant decrease in stress to nearzero on the metal lines if the interlayer oxides were deposited at 380°C. However, they further related the presence of metal extrusions tocontrolling the metal degas process to a temperature which is lower thanthat of the oxide deposition. This does not preclude a high level ofstress from being introduced during subsequent processes, and inparticular, during deposition of the relatively thin via-barrier layerwhich is the layer violated by the extruded metal.

[0038] According to this invention, the deposition temperature of thevia-barrier must be controlled to less than 400° C., and preferably tonear 380° C. It has been found that at CVD TiN deposition temperature of400° C., metal extrusions are not entirely eliminated; however, at 380°C. metal extrusions are completely eliminated. Heretofore, CVDdeposition temperature of TiN has typically been recommended by reactormanufacturers to be greater than 400° C.

[0039] Via test structures which allow resistance measurement of singlevias have been used to quantify the impact of reduction in titaniumnitride via barrier deposition temperature to approximately 380° C.Based on parametric data from a large number of process lots comparingthe via barrier deposition temperature, the resistance of those testdevices having via barrier deposition at 380° C. were near the targetvalue, with no out of range values, whereas the devices processed atgreater than 400° C. had a lower probability of meeting the targetvalue, and had a number of devices outside the acceptable range.

[0040] The preferred embodiment of this invention includes CVDdeposition of TiN via-barrier within the range of 380° C. to 390° C.This process has been accomplished without decreasing the reactorthroughput by reducing preheat time. Substrate temperature control, andreduction in preheat time are assisted by incorporating a heated N₂ gasimpingement of the wafer backside. The preheat technique is not asubject of the current invention, and alternate techniques may beequally effective in speeding the reactor throughput. This technique isoffered as one example.

[0041] The controlled temperature via-barrier process is described withrespect to a preferred embodiment, however it should be recognized thatit is applicable to alternate metallization stacks, including amongothers Ti/TiN, TiN, TiN/Ti on both conductor surfaces. The invention isnot restricted to a given barrier thickness, but further, it isapplicable to a variety of different materials, and via configurations.

[0042] For the specific via-barrier deposition temperature of 380° C.,it is expected that the interconnection metals of choice will be highexpansion materials such as aluminum, having a thermal coefficient ofexpansion (CTE) of about 26PPM, copper of about 17PPM, or various alloysthereof, which are considerably more thermally expansive that siliconand silicon dioxide having CTE in the range of 2.2 to 2.5 PPM. Foralternate material combinations, the deposition temperature of thevia-barrier would be controlled to one wherein the metal stress levelapproaches zero.

[0043] Thicker via barrier layers may add a margin of safety to theprocess, but are not a cure for aluminum extrusion into the via, whereascontrolling the deposition temperature of the via-barrier eliminates thecause, and thus provides a process for avoiding the presence of metalextrusions into the via hole.

[0044] Many variations and modifications of the described embodimentswill become apparent to those skilled in the art; it is therefore, theintent that the intended claims be interpreted as broadly as possible inview of prior art in order to include all such variations.

What is claimed is: 1- A method for making a multilevel integratedcircuit device without formation of metal extrusions into a viaincluding the steps of: providing a semiconductor substrate having adielectric layer, depositing a metal stack, patterning and etching toform interconnection lines, depositing one or more dielectric layers,patterning and etching the dielectric to form a via hole to contact aninterconnection line, depositing a seed layer and a via-barrier layer ata controlled temperature, low enough to substantially eliminate stresson the metal interconnection line, and filling the via hole with a metalplug. 2- A process as in claim 1 wherein said temperature of via barrierdeposition is controlled to between 380° C. and 390° C. 3- A process asin claim 1 wherein said metal stack comprises a conductive layer of analuminum alloy sandwiched between layers of titanium, and titaniumnitride in various combinations thereof. 4- A process as in claim 1wherein said metal stack includes reacted titanium aluminide. 5- Aprocess as in claim 1 wherein the dielectric comprises a silicondioxide, HDP, TEOS or other conformal dielectric coating. 6- A processas in claim 1 wherein said via-barrier is a CVD deposited TiN. 7- Aprocess as in claim 1 wherein the seed layer is Ti. 8- A process as inclaim 1 wherein said metal plug is CVD deposited tungsten. 9- A processas in claim 1 which further includes an antireflective coating on saidinterconnection lines conductor. 10- A process as in claim 8 whereinsaid antireflective coating comprises TiN. 11- A process as in claim 8wherein said antireflective coating comprises silicon oxynitride. 12- Anintegrated circuit device having a multi-level metallization structurethereon made using the process of claim 1.